Renesas Electronics /R7FA6T3BB /CANFD_B /CFDC0FDCFG

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Interpret as CFDC0FDCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)EOCCFG 0 (0)TDCOC 0 (0)TDCE 0 (0)ESIC 0TDCO0 (0)FDOE 0 (0)REFE 0 (0)CLOE

REFE=0, TDCE=0, ESIC=0, TDCOC=0, FDOE=0, CLOE=0, EOCCFG=000

Description

Channel 0 CANFD Configuration Register

Fields

EOCCFG

Error Occurrence Counter Configuration

0 (000): All transmitter or receiver CAN frames

1 (001): All transmitter CAN frames

2 (010): All receiver CAN frames

3 (011): Reserved

4 (100): Only transmitter or receiver CANFD data-phase (fast bits)

5 (101): Only transmitter CANFD data-phase (fast bits)

6 (110): Only receiver CANFD data-phase (fast bits)

7 (111): Reserved

TDCOC

Transceiver Delay Compensation Offset Configuration

0 (0): Measured + offset

1 (1): Offset-only

TDCE

Transceiver Delay Compensation Enable

0 (0): Transceiver delay compensation disabled

1 (1): Transceiver delay compensation enabled

ESIC

Error State Indication Configuration

0 (0): The ESI bit in the frame represents the error state of the node itself

1 (1): The ESI bit in the frame represents the error state of the message buffer if the node itself is not in error passive. If the node is in error passive, then the ESI bit is driven by the node itself.

TDCO

Transceiver Delay Compensation Offset

FDOE

FD-Only Enable

0 (0): FD-only mode disabled

1 (1): FD-only mode enabled

REFE

RX Edge Filter Enable

0 (0): RX edge filter disabled

1 (1): RX edge filter enabled

CLOE

Classical CAN Enable

0 (0): Classical CAN mode disabled

1 (1): Classical CAN mode enabled

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